Progressive miniaturization of semiconductor devices leads to scaling down of the structures of such devices. For example, gate lengths become shorter and shorter, e.g. less than 100 nm. With such short gate lengths the drain and the source of the device may start to interact independently of the gate, which deteriorates performance of the semiconductor device. This effect is called the “short channel effect”.
In order to counteract this effect, modem semiconductor devices comprising a first main electrode extension, such as e.g. a source, and a second main electrode extension, such as for example a drain, furthermore comprise a boundary region, such as e.g. a pocket or halo surrounding the first and second main electrode extension. It is important that these boundary regions have well defined properties. In particular, their position should be very close to the corresponding main electrode extension, which should be highly activated with the appropriate dopant and be very thin. Up to now, said boundary regions have been formed by implanting a certain dopant in the semiconductor substrate to a certain depth, followed by implanting and activating the desired dopant for the main electrode extensions.
A method to obtain highly activated regions in solid state devices is solid phase epitaxy regrowth (SPER). The technique is useful in the fabrication of highly activated, abrupt, ultra-shallow junctions for first and second main electrode extensions in MOSFET-devices. In particular, SPER is used to recrystallize regions of amorphous semiconductor material that has been doped with a dopant.
U.S. Pat. No. 6,521,502 describes a method of manufacturing source and drain junction extensions and halo regions using solid phase epitaxy activation. The method described comprises the steps of deep amorphization by means of ion implantation to form deep amorphous regions in the semiconductor substrate. Next, shallow source and drain extensions are formed via source and drain extension dopant implant. In a next step a tilted angle halo dopant implant is performed in order to form halo layers. Furthermore, dielectric spacers are formed and deep source and drain implants are performed. In a last step extensions, deep regions and halo regions are annealed, preferably by a solid phase epitaxy technique, to activate the dopants and to recrystallize the amorphized region.
A disadvantage of the method described above is that it is difficult to obtain full control of the halo as to position and profile of the activated dopant. It is very important to obtain a thin (a few nm), highly activated, abrupt and well-positioned, i.e. around the extensions, halo. Since it is very difficult to fulfill these requirements when implanting and performing a standard high temperature anneal, the sharpness and abruptness of the halos should be much improved to improve the performance of the semiconductor device.
Furthermore, it is a problem that the profiles of activated dopants for the halos and the extensions more or less overlap. It is very difficult to obtain layers of activated dopants with a well defined concentration profile and a very small thickness (less than 10 nm).